1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for isolating semiconductor devices.
2. Discussion of the Related Art
A shallow trench isolation process has been applied to a device isolating process enabling the removal factors of instability of a process. These factors of instability include heat treatment of a field oxide film according to reduction of a design rule of a semiconductor device. Application of a shallow trench isolation process also fundamentally solves a problem such as reduction of an active region according to a bird's beak. Shallow trench isolation is also predicted to be applied to a process of manufacturing a highly integrated semiconductor device of more than 1G DRAM or 4G DRAM.
In the STI process, a pad oxide film and a nitride film are formed on a silicon substrate. After a trench mask is formed by selectively etching the pad oxide film and the nitride film, a trench is formed by carrying out dry etching on the silicon substrate using the patterned nitride film as an etch mask. Subsequently, an oxide film for filing up the trench is deposited to fill the trench, and chemical mechanical polishing (CMP) is performed. Then, the pad oxide film and the pad nitride film are removed to form a device isolating film.
FIG. 1 and FIG. 2 illustrate cross sectional views showing a method for isolating semiconductor devices in accordance with a related art. As a semiconductor has been highly integrated, a width of a trench, that is, a device isolating region, has been reduced.
Accordingly, an aspect ratio has been relatively increased, thereby resulting in a difficulty in adequately filing in the trench.
FIG. 1 illustrates a diagram showing a void in a trench in accordance with a related art. As illustrated in FIG. 1, a liner oxide film 13 is formed on a surface of a trench 12 formed on a semiconductor substrate 11, and an isolation film 14 is vapor deposited on the liner oxide film 13 so as to fill the trench 12.
However, when a width of the trench 12 is reduced, the trench 12 may not be filled completely, forming the void in the isolation film 14. Accordingly, in a next process, the void becomes a source of leakage when a polysilicon film used as a gate material is filled in the void. In addition, when the void is large, it is difficult to isolate the devices. Therefore, a technology of reducing a depth of the trench more and more is demanded so as to reduce the aspect ratio.
FIG. 2 illustrates a diagram showing a related art device isolation structure having a trench with a reduced depth. As illustrated in FIG. 2, a device isolating film 22 with a trench structure for isolating between NMOSFETs on a P type substrate 21 isolates regions between a plurality of N type interfaces 23 of the NMOSFET, and the NMOSFET includes a P well 24.
As illustrated in FIG. 2, when a depth h of the trench is reduced, a leakage path is formed between adjacent NMOSFETs, thereby severely affecting reliability of the device.